1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits, and more specifically to a method for manufacturing complementary field effect devices (CMOS) in an integrated circuit.
2. Description of the Prior Art
In general, the industry continues to try to make integrated circuit devices smaller. Smaller chips, in general, are less expensive and often provide better performance. However, various problems related to the physical size of components on the integrated circuit become important as devices are scaled to smaller and smaller sizes.
Currently, local oxidation techniques are used to form field oxide regions between devices. Such techniques are often referred to as LOCal Oxidation of Silicon (LOCOS). In general, these techniques provide for covering active areas of the semiconductor chip with a protective oxide/nitride layer. This layer is removed where field oxide regions are to be grown, and a high temperature oxide is grown on the device. Oxide grows in the exposed regions, and not under the nitride layer. This technique causes the formation of the well known "bird's beak", which extends partway into the active areas surrounding the field oxide region.
As device scales continue to shrink, problems are encountered as a result of the bird's beak phenomenon. Various edge effects occur in channel regions located adjacent the bird's beak, which can cause significant performance problems in narrow width transistors. In order to avoid these edge effects, transistors cannot generally be made smaller than certain minimum sizes. These minimum allowable transistor sizes place limits on the spacing of devices within the integrated circuit, thereby limiting the device scaling which can be realized.
It would be desirable to provide a method for forming field oxide regions within an integrated circuit which does not cause edge effects within adjacent field effect devices, thereby allowing additional shrinkage in device feature sizes.